Integrated circuits are chemically and physically integrated into a substrate, such as a silicon wafer, by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication. They can also be of different conductivity types, which is essential for transistor and diode fabrication.
Deposited conductors are an integral part of every integrated circuit, and provide the role of surface wiring for conducting current. Specifically, the deposited conductors are used to wire together the various components that are formed in the surface of the wafer. Such conductors are commonly known as "lines" or "runners". Conductors also provide other functions in integrated circuit structures, such as fuses and backside electrical contacts for the packaged die.
The conductive lines or runners are preferably formed of a highly electrically conductive material, such as metal. Another common conductive material for producing the surface wiring effect is polysilicon (hereafter poly). A concern in forming poly lines or runners is to protect the immediate area on either side of the runner from the next implant step. FIG. 1 diagrammatically illustrates in an enlarged and exaggerated sectional view a doped poly runner 12 which has been provided atop a thin SiO.sub.2 layer 11 on a doped silicon substrate 10. A photoresist mask layer 14 is provided atop the poly and is dimensioned to have a greater width than the desired finished width of the poly runner. As illustrated, this leaves a resist overhang on either side of poly runner 12 due to the greater width of the resist layer compared to that of poly runner 12.
This structure can be provided by isotropically dry etching the poly within a parallel plate reactor. A desired chemically reactive gas mixture is provided within such a reactor, and the mixture energized to a plasma state. The chemically reactive mixture is designed to be reactive with the poly, but not the photoresist or the silicon dioxide layer atop the substrate. The effect is to etch the poly runner to a narrower width beneath photoresist 14, as indicated by isotropic etching lines A. The term "isotropic etch" is an accepted term within the semiconductor industry which indicates an etching process which removes unmasked material in both a downward and sideward direction, as shown. Conversely, the term "anisotropic etch" defines an etching process which doesn't attack the masked material from the side, but merely etches in a direction which is perpendicular to the work piece. The isotropic etch of FIG. 1 is relatively simple since there is just one material being etched, namely the poly. At the completion of the etch, the next layer of material would be applied, the resist would then be removed, and the wafer would continue on through other process steps.
As the size of the integrated circuit shrinks, the speed that the current flows along the conductive runners becomes a critical issue. One way of increasing the speed of a poly runner is to deposit a more highly conductive metal silicide layer atop the poly. Such a layered poly structure lowers the total resistance of the runner.
One such structure consists essentially of a layer of WSi.sub.x which overlies poly. The process of isotropically etching a WSi.sub.x /polysilicon sandwich is difficult because of the different etch characteristics of poly and tungsten (W). One of the usual outcomes of trying to etch both of these levels at the same time is presented in FIG. 2 where a tungsten layer 16 is etched at a faster rate than underlying poly layer 12. Dependent upon etch chemistry and etch processing parameters, the opposite problem is presented in FIG. 3 where the poly etch rate is much faster than the tungsten etch rate.
One of the ways that these problems have been overcome is by use of an anisotropic etch as illustrated in FIG. 4. Here, the resist is provided such that there would be no overhang of the finished width of the runner, with the anisotropic etch exemplified by lines B resulting in vertical sidewalls as illustrated. The resist would then be removed and the wafer passed through a spacer process to leave a small amount of oxide 18 on both sides of the conductive runner, as illustrated in FIG. 5. Oxide 18 acts as an implant block to provide the same function that a resist overhang does in an isotropic etch. However, this method involves several extra processing steps.
In some etching operations, it is desirable to achieve anisotropic etching and to operate at very high power densities on the parallel plates. However, photoresist masking can burn at these high power densities. Intermittent pulse reactors were developed to provide a high power anisotropic etch without etching away the photoresist in the process. This invention relates specifically to these types of etchers.
The primary manufacturer of intermittent pulse anisotropic plasma etchers is the Tegal Corp. of Petaluma, Calif. One of their reactors is the Tegal Model 1511e Plasma Reactor which spaces the parallel plates at a fixed distance from one another. Such a reactor is provided with operator controllable power pulsing in order to obtain the desired selective anisotropic etch, depending upon the material being etched and the plasma gas chemistry. When current is applied at a selected rate, an RF field directs ion radicals perpendicularly toward the work piece to achieve an anisotropic etch. Under high current density, the current is intermittently pulsed to an "off" condition to avoid burning away photoresist. This provides the operator with the ability to achieve the effects of high current density etching without removing photoresist.
In this document, the intermittent pulsing is referred to as being defined by an RFon period, an RFoff period, and an RFrepeat period. The "RFon" period is that time period during which the preselected amount of power is applied to the parallel plates. The "RFoff" period is that time period when a significantly reduced amount of power or no power is applied to the parallel plates. The RFrepeat period is the sum of a single RFon period and a single consecutively following RFoff period.
It is desirable that RFoff be as short as possible to minimize the etching treatment time, yet still achieve the high current anisotropic etch without removing photoresist. Tegal recommends and is able to achieve the desired etching in most instances with an RFon of 1.8 ms and RFoff of 0.2 ms, to provide an RFrepeat of 2.0 ms. This provides a ratio of RFon:RFrepeat of 0.90.
At this writing, their is no indication by the manufacturer or elsewhere in the prior art that such intermittent pulsing reactors might be operated to produce an isotropic etch, or how one might operate such a reactor to produce an isotropic etch.
One object of this invention is to isotropically dry etch a current conducting runner comprising polysilicon material with an intermittent pulse plasma reactor.
Another object of this invention is to produce an isotropic etching effect in a WSi.sub.x /polysilicon sandwich structure beneath a layer of photoresist to provide a photoresist overhang of the finished width WSi.sub.x /polysilicon width runner by using an isotropic etching process with such a reactor.